1. Field of the Invention
The present invention relates to a vertical PNP bipolar transistor and its method of fabrication. More particularly, it relates to a vertical PNP transistor fabricated without an epitaxial silicon layer therein.
2. Description of the Prior Art
Generally there are two types of bipolar transistors, i.e. a lateral bipolar transistor and a vertical bipolar transistor. In the lateral bipolar transistor, the current flows around a surface of the transistor, while in a vertical bipolar transistor the current flow is perpendicular to the plane of the substrate.
An example of a typical prior art vertical PNP bipolar transistor can be found with reference to U.S. Pat. No. 5,677,209 issued to Shon et al, incorporated herein by reference. This transistor is shown with reference to FIG. 1. Referring to FIG. 1, the vertical PNP transistor has a P-type semiconductor substrate 11. An N-type buried layer 13 is formed on an upper portion of the P-type substrate 11. A P-type epitaxial layer 15 which functions as a collector region is grown on the P-type substrate 11 having N-type buried layer 13 on a surface portion thereof. An N-type sink 16 is formed in epitaxial layer 15 from the surface of the epitaxial layer 16 to N-type buried layer 13 so that the N-type sink 16 overlaps (or contacts) N-type buried layer 13 to separate the elements of the vertical transistor in the horizontal direction by defining a P-type well 17 in epitaxial layer 15. A base mask 19 is formed with an opening 21 to expose a portion of P-type well 17 on the surface of epitaxial layer 15. A P-type collector enhancement region 23 is formed above N-type buried layer 13 by implanting a dopant through opening 21 of base mask 19. An N-type base region 25 is formed above collector enhancement region 23 by implanting a dopant through opening 21 of base mask 19. A polysilicon emitter contact region 27 is formed on a portion of base region 25. A P-type emitter region 29 is formed under emitter contact region 27 and at an upper portion of base region 25 by diffusing the dopant from emitter contact region 27. An N-type base contact region 31 is formed at another upper portion of base region 25, and a plurality of collector contact regions 33 and 34 are formed at surface portions of P-type well 17 except the portion where base region 25 is formed.
While there have been many variations of vertical PNP transistors, they all have had one thing in common. That is, all of the prior art transistors of this type have required the use of an epitaxially grown layer in their fabrication, usually an epitaxial N-type isolation layer.
Wireless communication circuits continue to progress toward higher speed and higher integration in an effort to reduce cost and increase performance. However, processing technology must be developed to address this need for high speed with low power and low cost devices. One approach to the problem is the fabrication of BiCMOS structures. These structures have both bipolar transistors for power or high voltage capabilities, and CMOS devices for digital or logical capabilities. The transistors in a bipolar or BiCMOS process must have a highly conductive P-type collector layer which is isolated from the P-type substrate by an N-type isolation layer. Heretofore, such structures have been achieved utilizing low to medium energy ion implantation followed by the growth of an epitaxial silicon isolation layer. Examples of such structures and processing to achieve them can be found in xe2x80x9cA Complementary Bipolar Technology for Low Cost and High Performance Mixed Analog/Digital Applicationsxe2x80x9d, H. Miwa et al., IEEE BCTM 11.4 Tech. Digest, 185-188, (1996) and xe2x80x9cProcess HJ: A 30 GHz NPN and 20 GHz PNP Complementary Bipolar Process for High Linearity RF Circuitsxe2x80x9d, M. C. Wilson et al., IEEE BCTM 9.4 Tech. Digest, 164-167 (1998) incorporated herein by reference.
It would be highly desirable to be able to fabricate such a transistor without the need for epitaxial silicon growth and in a manner that is compatible with the fabrication of the CMOS device. Elimination of the epitaxial processing step should result in low cost devices with high yield and which are relatively easy to manufacture.
A high performance complementary bipolar vertical PNP transistor especially useful in a CMOS device comprises, a P-type silicon substrate, a PNP-tub, a P-tub adjacent the PNP-tub, said PNP-tub having a p+ collector implanted therein, said PNP-tub having an N-type isolation layer implanted therein and an n+ base and a p+ emitter spaced from the n+ base implanted in the N-type isolation layer, said N-type isolation layer being spaced from the collector in the P-tub and isolated therefrom with a dielectric isolation layer deposited therebetween, the transistor being devoid of any epitaxial layers.
In a preferred embodiment wherein the transistor is integrated with a CMOS device, the transistor further includes a first and a second N-tub adjacent the PNP-tub and P-tub, respectively, each N-tub having a dielectric isolation layer deposited thereover to provide lateral isolation of the PNP transistor from adjacent CMOS devices.
A key to the formation of the high performance bipolar vertical PNP transistor of the present invention is the step of providing a substrate isolation layer of the transistor by High energy phosphorus ion implantation rather than the formation of an N-type epitaxially grown layer.